1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a method of testing a semiconductor device which is equipped with a timing-stabilization circuit such as a DLL (delay-locked loop) circuit or a PLL (phase-locked loop) circuit.
2. Description of the Related Art
A semiconductor device operating at a high speed is generally equipped with a timing-stabilization circuit such as a DLL/PLL circuit to achieve stable distribution of an external clock to internal circuits. The timing-stabilization circuit is also used for such purposes as improving conditions of a set-up time, a hold time, and a data-access time of the semiconductor device in addition to a purpose of supplying a stable synchronization signal to internal circuits.
The timing-stabilization circuit needs a certain time period (lock-on time) from the time of reception of an input signal before completing stabilization of internal signals by locking on to the input signal. At the time of switching on of a semiconductor device or at the time of a mode transition from a power-down mode for power conservation to a battery-back-up mode or to an active mode, the timing-stabilization circuit first switches from an inactive state to an active state before locking on, and, thus, a required time period before the locking on varies. It is vital to take an accurate measurement of the lock-on time with respect to such a case, therefore, in order to know an exact tolerance level of the timing-stabilization capacity of the semiconductor device.
FIG. 1 is a flowchart of a related-art method of measuring a lock-on time of a timing-stabilization circuit at the time when a semiconductor memory device is switched on.
In order to measure the lock-on time, a check has to be made as to whether the timing-stabilization circuit has locked on or not. The related-art method of FIG. 1 makes this check by using an access time of the semiconductor memory device. In advance, an access time is measured as a time period from the input of a read command to the output of data. This measurement is taken while the timing-stabilization circuit is locking on. When the timing-stabilization circuit is not locking on, the access time becomes longer than that in the lock-on state. A check thus can be made as to whether the timing-stabilization circuit is locking on by finding whether the access time is extended.
At a step S1, the number of clock pulses are counted as to how many clock pulses are necessary for a timing-stabilization circuit of a semiconductor memory device to lock on, and this number is denoted as n. For example, when it is found that the timing-stabilization circuit reliably locks on after receiving 1000 clock pulses, the number n is set to 1000.
At a step S2, the semiconductor memory device is powered on by supplying a power voltage VCC to the semiconductor memory device.
At a step S3, n clock pulses are input to make the timing-stabilization circuit lock on.
At a step S4, a timing of a data strobe STRB is set to 0 ns so as to correspond to a timing at which a read command is input to the semiconductor memory device. The data strobe STRB is a pulse used by a tester for detecting data so that the tester can latch the data read from the semiconductor memory device.
At a step S5, a read command is input by the tester to the semiconductor memory device, and a check is made whether the read data is latched by using the data strobe STRB. If the data is latched, it is ascertained that the access test has succeeded, and the procedure goes to a step S7. If the data is not latched, it is ascertained that the access test has failed, and the procedure goes to a step S6.
At the step S6, the data strobe STRB is delayed by a predetermined delay time, for example, by 0.1 ns. Then, the access test at the step S5 is repeated.
The timing of the data strobe STRB is delayed step by step at the step S6. When the data strobe STRB is finally set to a timing that allows the read data to be latched, it is ascertained that the access test has succeeded. That is, the timing of the data strobe STRB indicates an access time under the condition that the timing-stabilization circuit is locking on, i.e., indicates a time period from the input of the read command to the output of the data.
At the step S7, the timing of the data strobe STRB is stored as an access time ACO under the lock-on condition of the timing-stabilization circuit. In the following steps, the access time ACO will be used for measuring a time period that is required by the timing-stabilization circuit to lock on.
At a step S8, the number n of clock pulses is set to zero.
At a step S9, the timing of the data strobe STRB is set to 0 ns.
At a step S10, the power of the semiconductor memory device is cut, and the procedure waits for internal voltages to be discharged. Namely, after the power cut, the procedure waits 10 seconds, for example, before carrying out a next step.
At a step S11, the power voltage VCC is supplied to the semiconductor memory device.
At a step S12, n clock pulses are input.
At a step S13, a read command is input by the tester to the semiconductor memory device, and a check is made whether the read data is latched by using the data strobe STRB. If the data is latched, it is ascertained that the access test has succeeded, and the procedure goes to a step S15. If the data is not latched, it is ascertained that the access test has failed, and the procedure goes to a step S14.
At the step S14, the data strobe STRB is delayed by a predetermined delay time, for example, by 0.1 ns. Then, the procedure goes back to the step S10 to repeat the steps S10 through S13.
The timing of the data strobe STRB is delayed step by step at the step S14. When the data strobe STRB is finally set to a timing that allows the read data to be latched, it is ascertained that the access test has succeeded. That is, the timing of the data strobe STRB indicates an access time under the condition that the timing-stabilization circuit has received n clock pulses.
At the step S15, the timing of the data strobe STRB is stored as an access time ACn under the condition that the timing-stabilization circuit has received n clock pulses.
At a step S16, a comparison is made between the access time ACn and the access time ACO which is an access time under the lock-on condition of the timing-stabilization circuit. If a difference between these access times is smaller than a predetermined threshold (e.g., 0.2 ns), the procedure goes to a step S18. Otherwise, the procedure goes to a step S17.
At the step S17, the number n of clock pulses is incremented by one. The procedure goes back to a step S9 to repeat the steps S9 through S16.
At the step S18, a lock-on time is obtained as n.times.tCLK by using n as the number of lock-on cycles based on the understanding that the timing-stabilization circuit locks on when n clock pulses are input. Here, tCLK denotes a cycle of the clock signal. This ends the procedure with measurement of the lock-on time being completed.
FIG. 2 is a flowchart of a related-art method of measuring a lock-on time of a timing-stabilization circuit at the time when a semiconductor memory device is reactivated (by returning from the power-down mode, for example).
The flowchart of FIG. 2 differs from the flowchart of FIG. 1 only in that the step S10 is divided into steps S10-1 through S10-3. At the step S10-1, the timing-stabilization circuit is prompted to lock on. At the step S10-2, the timing-stabilization circuit is deactivated, and changes are made to the power voltage VCC and/or temperature, etc. At the step S10-3, the timing-stabilization circuit is reactivated. By incorporating these steps, measurement of the lock-on time can be made with regard to a case in which the timing-stabilization circuit is reactivated after changes in various conditions are made during the period of inactivation. It should be noted that the step S14 includes, in addition to delaying the data strobe STRB, a step of returning the power voltage VCC and/or temperature, etc., to original conditions as they were before the inactivation.
According to the above procedures, the lock-on time can be measured with respect to a case of switching on of the timing-stabilization circuit and a case of reactivation of the timing-stabilization circuit. Since the steps S9 through S16 should be performed many times by gradually changing the number of input clock pulses, the test is quite time consuming. When there is a need to measure lock-on times under various conditions in terms of the power voltage VCC and the clock cycle tCLK, the above procedures needs to be repeated many times by changing the power voltage VCC and the clock cycle tCLK. This further extends the total test time. Further, the step S10 described above includes waiting for the internal voltages to be discharged after the power cut. This also adds to the total test time.
Accordingly, there is a need for a method of measuring a lock-on time of a timing-stabilization circuit in a short time for a semiconductor device.